Publication

International Journals (Regular)

- Imjae Hwang, Hyuck-Joo Kwon, Ji-Hye Chang, Yeongkyu Lim, Cheong Ghil Kim, and Woo-Chan Park, "An Effective Viewport Resolution Scaling Technique to Reduce the Power Consumption in Mobile GPUs," KSII Transactions on Internet and Information Systems, Vol. 11, No. 8, pp. 3918-3934, Aug 2017

- Dong-Seok Kim, Jae-Ho Nah, and Woo-Chan Park, "Geometry transition method to improve ray-tracing precision," Multimedia Tools and Applications, Vol.75, No. 10, pp. 5689-5700, May 2016 

-  Jae-Ho Nah, Jin-Woo Kim, Junho Park, Won-Jong Lee, Jeong-Soo Park, Seok-Yoon Jung,  Woo-Chan Park, Dinesh Manocha, and Tach-Don Han, "HART: A Hybrid Architecture for Ray Tracing Animated Scenes," IEEE Transactions on Visualization and Computer Graphics, Vol. 21, No.3, pp. 389-401, March 2015

- Jae-Ho Nah, Hyuck-Joo Kwon, Dong-Seok Kim, Cheol-Ho Jeong, JinHong Park, Tack-Don Han, Dinesh Manocha, and Woo-Chan Park, "RayCore: A ray-tracing hardware architecture for mobile devices," ACM Transactions on Graphics, Vol. 33, No. 5, Article 162, Aug 2014

- Hyuck-Joo Kwon, Jae-Ho Nah, Dinesh Manocha, and Woo-Chan Park, "Effective traversal algorithms and hardware architecture for pyramidal inverse displacement mapping," Computers & Graphics, Vol. 38, No. 22, pp. 140-149, Feb 2014

- Jae-Ho Nah, Woo-Chan Park, Yoon-Sig Kang, and Tack-Don Han, "Ray box culling for tree structures," Journal of Information Science and Engineering, Vol. 29, No. 6, pp. 1211-1225, November 2013.

- Jeong-soo Park, Woo-Chan Park, Jae-Ho Nah, and Tack-don Han, "Node pre-fetching architecture for real-time ray tracing, IEICE Electronics Express, Vol. 10, No. 14, pp.1-6, July 2013.

- Yong-Jin Park, Woo-Chan Park, Jun-Hyun Bae, Jin-hong Park, and Tack-Don Han, "Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors," IEICE TRANSACTION on Information and Systems, Vol. E96-D, No. 7, pp. 1443-1448, July 2013.

- Jin-hong Park, Il-San Kim, Woo-Chan Park, Yong-Jin Park, and Tack-Don Han, "A Pixel Pipeline Architecture with Selective Z-Test Scheme for 3D Graphics Processors," Microprocessors and Microsystems, Vol. 37, No. 3, pp.373-380, May 2013.

- Yoon-Sig Kang, Jae-Ho Nah, Woo-Chan Park, and Sung-Bong Yang, "gkDtree : A Group-Based Parallel Update Kd-tree for Interactive Ray Tracing," Journal of Systems Architecture, Vol. 59, No. 3, pp.166-175, March 2013.

- Jae-Ho Nah, Yun-Hye Jung, Woo-Chan Park, and Tack-Don Han, "Efficient ray sorting for the tracing incoherent rays," IEICE Electronics Express, Vol. 9, No. 9, pp.849-854, May 2012.

- Jae-Ho Nah, Jeong-Soo Park, Chanmin Park, Jin-Woo Kim, Yun-Hye Jung, Woo-Chan Park, and Tack-Don Han, "T&I Engine: Traversal and Intersection Engine for Hardware Accelerated Ray Tracing," ACM Transactions on Graphics, Vol. 30, No. 6, Article 160, Dec. 2011.

- Hong-Sik Kim, Joohong Lee , Hyunjin Kim, Sungho Kang, and Woo Chan Park, "A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware Codec," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 21, No. 11, pp. 1581-1587, Nov. 2011.

- Woo-Chan Park, Dong-Seok Kim, Jeong-Soo Park, Sang-Duk Kim, Hong-Sik Kim and Tack-Don Han, "The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing," IEICE Electron. Express, Vol. 8, No. 13, pp.1064-1070, July 2011.

- Jinhong Park, Jinwoo Kim, Woo-Chan Park, Youngsik Kim, Chelho Jeong and Tack-Don Han, “An effective rasterization architecture for mobile vector graphics processors,” IEICE Electronics Express, Vol. 8, No. 11, pp.835-841, June 2011.

- Woo-Chan Park, Jin-Hong Park, Woo-Nam Chung, Jeong-Soo Park, Sang-Duk Kim, Hong-Sik Kim, Young-Sik Kim and Tack-Don Han, “An effective depth data memory system using an escape count buffer for 3D rendering processors,” IEICE Electron. Express, Vol. 8, No. 4, pp.209-214, Feb. 2011.

- Woo-Chan Park, Duk-Ki Yoon, Dong-Seok Kim, Hong-Sik Kim, Jin-Hong Park, Woo-Nam Jeong, and Tack-Don Han, "The design of compressed memory system for depth data in 3D rendering processors," IEICE Electronics Express, Vol. 7, No. 21, pp. 1622-1628, Nov. 2010.

- Hong-Sik Kim, Youngha Jung, Hyunjin Kim, Jin-Ho Ahn, Woo-Chan Park and Sungho Kang, “A high performance network-on-chip scheme using lossless data compression,” IEICE Electron. Express, Vol.7, No.11, pp.791-796, May 2010.

- Won-Jong Lee, Vason P. Srini, Woo-Chan Park, Shigeru Muraka, and Tack-Don Han, "An Effective Load Balancing Scheme for 3D Texture- based Sort-Last Parallel Volume Rendering on GPU Clusters," IEICE Transactions on Information and Systems, Vol. E91-D, No.3, pp.846-856, March 2008.

- Won-Jong Lee, Woo-chan Park, Vason P. Srimi, Tack-Don han, "Simulation Development Environment for Mobile 3D Graphics Architectures," IET Computers & Digital Techniques, Vol. 1, No.5, pp.501-507, Sept 2007.

- Woo-Chan Park, Cheong-Gil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han, "A Consistency-free Memory Architecture for Sort-last Parallel Rendering Processors," Journal of Systems Architecture, Vol. 53, issues5, pp. 272-284, May 2007.

- Seung-Gi Lee, Woo-Chan Park, Won-Jong Lee, Sung-Bong Yang, and Tack-Don Han, " An Effective Bump Mapping Hardware Architecture Using Polar Coordinate System," Journal of Information Science and Engineering, Vol. 23, No.2, pp.569-588, March 2007.

- Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavi, Tack-Don Han, and Shin-Dug Kim, "An Effective Visibility Culling Method Based on Cache Block," IEEE Transactions on Computers, Vol. 55, No. 8, pp 1024-1032, Aug. 2006.

- Byung-Uck Kim, Kyoung-Wha Kim, Woo-Chan Park, Sung-Bong Yang, and Tack-Don Han, "A Simple and Efficient Triangle Strip Filtering Algorithm," Journal of Information Science and Engineering, Vol.21, No.6, pp. 1227-1288, Nov. 2005.

- Kil-Whan Lee, Woo-Chan Park, Il-San Kim, and Tack-Don Han, "A Pixel Cache Architecture with Selective Placement Scheme based on Z-test Result," Microprocessors and Microsystems, Vol. 29, Issue 1, pp. 41-46, Feb. 2005.

- Byung-Uck Kim, Woo-Chan Park, Francis Neelamkavil, and Sung-Bong Yang, "A Rendering-Efficient Progressive Transmission of 3D Meshes," IEICE Transactions on Information and Systems, Vol. E89-D, No. 10, pp. 2399-2407, Oct. 2004.

- Jong-Chul Jeong, Woo-Chan Park, Woong Jeong, Moon-Key Lee, and Tack-Don Han, “A Cost-Effective Pipelined Divider with a Small Lookup Table,” IEEE Transactions on Computers, Vol. 53, No. 4, pp. 489-495, April 2004.

- Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, and Sung-Bong Yang, "An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors," IEEE Transactions on Computers, Vol. 52, No. 11, pp. 1501-1508, Nov. 2003.

- Cheol-Ho Jung, Woo-Chan Park, Tack-Don Han, Sung-Bong Yang, and Moon-Key Lee, "An Effective Out-of-order Execution Control Scheme for an Embedded Floating Point Coprocessor," Microprocessors and Microsystems, Vol. 27, Issue 4, pp. 171-180, April 2003.

- Woo-Chan Park, Cheol-Ho Jeong, and Tack-Don Han, "Design of the Floating Point Adder Supporting the Format Conversion and the Rounding Operations with Simultaneous Rounding Scheme," IEICE Transactions on Information and Systems, Vol. E85-D, No. 8, pp. 1341-1345, Aug. 2002.

- Woo-Chan Park, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang, "Floating Point Multiplier Performing IEEE Rounding and Addition in Parallel," Journal of System Architecture, Vol 45, Issue 14, pp. 1195-1207, June 1999.

- Woo-Chan Park, Shi-Wha Lee, Oh-Young Kown, Tack-Don Han, and Shin-Dug Kim, "Floating Point Adder/Subtractor Performing IEEE Rounding and Addition /Subtraction in Parallel," IEICE Transactions on Information and Systems, Vol. E79-D, No. 4, pp. 297-305, April 1996.

 

International Journals (LNCS)

- Woo-Chan Park. Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Kyung-Su Kim, Won-Jong Lee, Tack-Don Han, and Sung-Bong Yang, "A Processor Architecture with Effective Memory Systemfor Sort-Last Parallel Rendering," ARCS 2006, LNCS 3894, pp. 160-175, 2006

- Woo-Chan Park, Tack-Don Han, and Sung-Bong Yang, "A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel," Lecture Notes in Computer Science, Vol. 3189, pp. 568-581, Sept. 2004.

- Woo-Chan Park, Tack-Don Han, and Sung-Bong Yang, "Order Independent Transparency for Image Composition Parallel RenderingMachines," Lecture Notes in Computer Science, Vol. 3189, pp. 449-460, Sept. 2004.

- Byung-Uck Kim, Woo-Chan Park, Sung-Bong Yang, and Tack-Don Han, "Cost-Effective Supersampling for Full Scene Antialiasing Algorithm," Lecture Notes in Computer Science, Vol. 3189, pp. 271-281, Sept. 2004.

- Won-Jong Lee, Woo-Chan Park, Jung-Woo Kim, Tack-Don Han, Sung-Bong Yang, and Francis Neelamkavil, "A Bandwidth Reduction Scheme for 3D Texture-Based Volume Rendering on Commodity Graphics Hardware," Lecture Notes in Computer Science, Vol. 3044, pp. 741-750, May 2004.

- Won-Jong Lee, Hyung-Rae Kim, Woo-Chan Park, Jung-Woo Kim, Tack-Don Han, and Sung-Bong Yang, "A New Bandwidth Reduction Method for Distributed Rendering Systems," Lecture Notes in Computer Science, Vol. 2510, pp. 387-394, October 2002.

 

International Conferences

- Dukki Hong, Seiyoung Lee and Woo-Chan Park, "Real-time Sound Propagation Hardware Accelerator for Immersive Virtual Reality 3D Audio", ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games(I3D), San Francisco, CA, February. 2017.(Poster paper)

- Dukki Hong, Seiyoung Lee and Woo-Chan Park "3D Audio Down-Mixing System for Immersive Realistic Virtual Reality," The 2nd International Conference on Electronics, Electrical Engineering, Computer Science : Innovation and Convergence, Vol. 2, pp. 15-16, August. 2016

- Juwon Yun, Dukki Hong, Cheng Ghill Kim and Woo-Chan Park "The design of a Software Development Kit for Virtual Reality 3D Audios," The 2nd International Conference on Electronics, Electrical Engineering, Computer Science : Innovation and Convergence : Innovation and Convergence, Vol. 2, pp. 44-45, August. 2016

- Dukki Hong, Hyuck-Joo Kwon, Juwon Yun, and Woo-Chan Park "Audio Down-Mixing Hardware Based on Sound-tracing," COOL Chips XIX IEEE Symposium on Low-Power and High-Speed Chips, April. 2016. (Poster paper)

- Jaesin Lee, Imjae Hwang, Minji Lee, Dukki Hong and Woo-Chan Park, "An Effective Lossless Embedded Compressor for UHD," COOL Chips XIX IEEE Symposium on Low-Power and High-Speed Chips, April. 2016. (Poster paper)

- Du Yeon Oh, Hyuck-Joo Kwon, Woo Chan Park and Yeong Kyu Lim "Frame Rate Scaling Technique to Reduce Power Consumption in Mobile Virtual Reality Game," The 1st International Conference on Electronics, Electrical Engineering, Computer Science : Innovation and Convergence : Innovation and Convergence, Vol. 1, pp. 140-142, January. 2016

- Ji-Hey Chang, Hyuck-Joo Kwon, Woo Chan Park and Yeong Kyu Lim "A Study on the Effective Viewport Resolution Scaling of the Hardware Scaler Technique to Reduce Power Consumption in Mobile GPU," The 1st International Conference on Electronics, Electrical Engineering, Computer Science : Innovation and Convergence : Innovation and Convergence, Vol. 1, pp. 143-144, January. 2016

- Woo-Chan Park, Hee-Jin Shin, Byoungok Lee, Hyungmin Yoon, and Tack-Don Han, "RayChip: Real-time Ray Tracing Chip for Embedded Applications," HotChips (Symposium on High Performance Chips), August. 2014.

- Dukki Hong, Youngduke Seo, Youngsik Kim, Kwon-Taek Kwon, Sang-Oak Woo, Seok-Yoon Jung, Kyoungwoo Lee, Woo-Chan Park, "Effective Non-Blocking Cache Architecture for High-Performance Texture Mapping," MeAOW, October. 2013.

- Woo-chan Park, Jae-ho Nah, Jeong-soo Park, Kyung-ho Lee, Dong-seok Kim, Sang-duk Kim, Jin-hong Park, Yoon-sig Kang, Sung-bong Yang, and Tack-don Han, "An FPGA Implementation of Whitted-style Ray Tracing Accelerator," IEEE Symposium on Interactive Ray Tracing, August. 2008. (Poster paper)

- Jae-ho Nah, Jin-suk Heo, Woo-chan Park, and Tack-don Han, "A Split Node Cache Scheme for Fast Ray Tracing," IEEE Symposium on Interactive Ray Tracing, August. 2008. (Poster paper)

- Kyungho Lee, Sangduk Kim, Jaeho Nah, Yoon-Sig Kang, Dongseok Kim, Sang-Won Ha, Sung-Bong Yang, Tack-Don Han, and Woo-Chan Park, "A Framework for Real Time Ray Tracing," COOL CHIPS X IEEE Symposium on Low-Power and High-Speed Chips, April. 2007. (Poster paper)

- Seung-Gi Lee, Woo-Chan Park, Won-Jong Lee, Tack-Don Han, and Sung-Bong Yang, "An Effective Hardware Architecture for Bump Mapping Using Angular Operation," SIGGRAPH/EUROGRAPHICS Graphics Hardware Workshop 2003, pp. 68-75, July 2003.

- Cheol-Ho Jeong, Woo-Chan Park, Jong-Chul Jeong, Hyun-Jae Woo, Kil-Whan Lee, Won-Jong Lee, Il-San Kim, Seung-Gi Lee, Jae-Hyun Kim, Tack-Don Han, and Moon-Key Lee, "EmDavid: an Embedded 3D Graphic Accelerator for Mobile Devices," Cool Chips VI, pp. 72, April 2003.

- Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, and Sung-Bong Yang, "A mid-texturing pixel rasteriation pipeline architecture for 3D rendering processors," IEEE 13th international conference on application-specific systems, architectures and processors, pp. 173-182, July 2002.

- Cheol-Ho Jeong, Woo-Chan Park, Sang-Woo Kim, Tack-Don Han, and Moon-Key Lee "In-order issue out-of-order execution floating point coprocessor for CalmRISC32," IEEE 15th international symposium on computer arithmetic, pp. 195-200, June. 2001.

- Woo-Chan Park, Kil-Whan Lee, Seung-Gi Lee, Moon-Hee Choi, Won-Jong Lee, Cheol-Ho Jeong, Byung-Uck Kim, Woo-Nam Jung, Il-San Kim, Won-Ho Chun, Won-Suk Kim, Tack-Don Han, Moon-Key Lee, Sung-Bong Yang, and Shin-Dug Kim, "A high performance 3D graphics rasterizer with effective memory structure," COOL Chip IV, pp. 98-108, April. 2001.

- Woo-Chan Park, Tack-Don Han, Shin-Dug Kim, "Efficient simultaneous rounding method removing sticky-bit from critical path for floating point addition," AP-ASIC 2000, pp. 223-226, Aug. 2000.

- Cheol-Ho Jeong, Woo-Chan Park, Sang-Woo Kim, and Tack-Don Han, "The design and implementation of CalmRISC32 floating point unit," AP-ASIC 2000, pp. 327-330, Aug. 2000.

- Seung-Gi Lee, Woo-Chan Park, Won-Jong Lee, Woo-Nam Jung, and Tack-Don Han, "The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology," AP-ASIC 2000, pp. 219-222, Aug. 2000.

 

Patents

- United Stated Patent, 7,042,462, "Pexel Cache, 3D Graphic Accelerator Using It, and Method Therefor," May.9, 2006.

- United Stated Patent, 6,839,060, “Method and Device of Consistency Buffer For High Performance 3D Graphics Accelerator,” Jan.4, 2005.

- United Stated Patent, 6,791,558, “Method and Apparatus for Processing Pixel Rasterization in Three-Dimensional Rendering Processor,” Sept. 14, 2004.

- United Stated Patent, 6,785,701, “Apparatus and Method of Performing Addition and Rounding Operation in Parallel for Floating-Point Arithmetic Logic Unit,” Aug. 31, 2004.

- United Stated Patent,6,570,565, "3D Graphics Accelerator and Method for Processing Graphics Acceleration Using the Same," May 27, 2003.

- United Stated Patent, 6,269,385, " Method and Apparatus for Performing Simultaneously Addition and Rounding in a Floating Point Multiplier, " July 31, 2001.


Patents Applications

- United Stated Patent, 20,060,098,021, "Graphics System and Memory Device for Three-dimensional Graphics Acceleration and Method for Three Dimensional Graphics Processing," May.11, 2006.

- United Stated Patent, 10/231,566, “A New Pipelined Divider with a Small Lookup Table,” Aug. 2002.